This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to the manufacture and testing of static random access memories (SRAMs).
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems. Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM but also in SRAM realized as “stand-alone” memory integrated circuit devices. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-by-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.
Bias temperature instability (BTI) transistor degradation mechanisms have recently become observable at the extremely small minimum feature sizes in modern integrated circuits. One such mechanism is negative bias temperature instability (“NBTI”), which appears as an increase in threshold voltage over time, primarily in p-channel MOS transistors. The physical mechanism underlying NBTI is the trapping of charge at the gate dielectric interface that occurs over time in p-channel MOS transistors that are biased to an “on” state (i.e., a negative voltage at the transistor gate relative to its channel region). Conversely, positive bias-temperature instability (“PBTI”) is a similar degradation effect that primarily affects n-channel MOS transistors biased to an “on” state (i.e., a positive voltage at the transistor gate relative to its channel region). For MOS transistors with silicon dioxide gate dielectrics, only slight PBTI degradation of n-channel transistors has been observed in comparison to NBTI degradation of p-channel transistors in the same circuits.
Recently, however, the continuing demand for ever-smaller device geometries has led to the more widespread use of high-k gate dielectric films (i.e., gate dielectric materials with a high dielectric constant relative to that of silicon dioxide). These high-k gate dielectric films, which enable the formation of thicker gate dielectrics with excellent gate characteristics, are typically used in conjunction with metal gate electrodes, rather than polysilicon gates, due to such effects as polysilicon depletion. A common high-k dielectric film used in the art is hafnium oxide (HfO2). Examples of the metal gate material in modern device technologies include titanium nitride (TiN), tantalum-silicon-nitride (TaxSiyN), and tantalum carbide (TaCx). These high-k metal gate n-channel MOS transistors have been observed to be vulnerable to threshold voltage shifts due to PBTI, even though their conventional gate dielectric n-channel devices are not. This vulnerability is believed due to the affinity of HfO2 films to trap electrons under positive gate bias (relative to the transistor channel region). As in the case of NBTI, the effect of PBTI on high-k metal gate n-channel MOS transistors is an increase in threshold voltage over time.
In the context of CMOS SRAMs, BTI degradation affects the ability of memory cells to retain data, and to be written and read. These degradation effects will be described in connection with an example of a conventional SRAM cell as shown in FIG. 1. In this example, SRAM cell 2 is a conventional six-transistor (6-T) static memory cell 2, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 2 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 2 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor 3a and n-channel driver transistor 4a, and the other inverter of series-connected p-channel load transistor 3b and n-channel transistor 4b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 3a, 4a constitutes storage node SNT, and the common drain node of transistors 3b, 4b constitutes storage node SNB, in this example. N-channel pass-gate transistor 5a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass-gate transistor 5b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass-gate transistors 5a, 5b are driven by word line WLj for this jth row in which cell 2 resides.
In its normal operation, bit lines BLTk, BLBk are typically precharged by precharge circuitry 7 to a high voltage Vddp (which is at or near power supply voltage Vdda) and are equalized to that voltage; precharge circuitry 7 then releases bit lines BLTk, BLBk. To access cell 2 for a read operation, word line WLj is then energized, turning on pass-gate transistors 5a, 5b, and connecting storage nodes SNT, SNB to the then-floating bit lines BLTk, BLBk, respectively. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of the then-floating bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 2 to latch in the desired state.
BTI degradation can cause operational failures in SRAM cells that are already vulnerable due to variability and mismatch of sub-micron minimum feature size transistors, and other factors. In the conventional cell of FIG. 1, NBTI can affect p-channel load transistors 3a, 3b, while PBTI affects n-channel driver transistors 4a, 4b and n-channel pass transistors 5a, 5b. Typically, BTI appears at those transistors that are biased “on” for long periods of time, such as transistors 3b, 4a (biased on to retain a “0” data state of storage node SNT low and storage node SNB high) or transistors 3a, 4b (biased on to retain a “1” data state of storage node SNB low and storage node SNT high). While pass transistors 5a, 5b are also vulnerable to PBTI, the duty cycle at which these devices are biased on is much lower than for the inverter transistors. Both NBTI and PBTI are reflected by increases in transistor threshold voltage over operating life, which manifests as cell failures in later operating life.
One type of failure that can be caused by BTI is a read stability failure, also referred to as a “disturb” failure or as insufficient static noise margin, in which noise appearing as an elevated voltage (e.g., 0.2 volts) at the low storage node causes a false change of state of the cell. More specifically, this mechanism occurs in “half-selected” cells (cells in unselected columns of the selected row), upon the pass transistor passing the precharged bit line voltage to the low side storage node. If the low side driver transistor is not able to hold a sufficiently low voltage at the storage node, this noise can be of sufficient magnitude to trip the inverters of the cell. Read stability failures can occur in cases in which the drive of the SRAM cell driver or load transistors is mismatched relative to other transistors in the cell. For the example in which cell 2 of FIG. 1 is storing a “0” state (storage node SNT low and storage node SNB high) and has been storing this state for a long period of time, a positive voltage will have been present at the gate of driver transistor 4a over that time potentially causing a threshold voltage shift due to PBTI. If the threshold voltage of driver transistor 4a has increased due to PBTI, it will have weakened drive relative to its pass transistor 5a, which changes the operating point of the voltage divider of transistors 4a, 5a when transistor 5a is turned on during an access to row j. The voltage at storage node SNT during an access to a cell 2 in row j will thus shift to a higher than optimal voltage. This higher voltage will tend to turn on driver transistor 4b, which would flip the state of cell 2.
Conversely, a long-held “0” data state of cell 2 can cause NBTI degradation at load transistor 3b, increasing its threshold voltage relative to that of load transistor 3a. The resulting degradation in drive strength of load transistor 3b will reduce its ability to hold storage node SNB to a high voltage during a noise event, which also decreases the static noise margin of cell 2 and increases the likelihood of an undesired change of state.
As discussed above, a read of cell 2 is performed by energizing word line WLj to turn on pass transistors 5a, 5b, and sensing which of precharged bit lines BLTk, BLBk are pulled down by the driver transistor 4a, 4b current in its “on” state. Similarly, weakening of the drive of one of driver transistors 4a, 4b, and of one of load transistors 3a, 3b, due to PBTI and NBTI, respectively, results in weaker read current during a read cycle. Sufficiently weak read current will, of course, causes an insufficient differential signal to be developed across bit lines BLTk, BLBk, leading to a so-called “read failure” (an incorrect data state being read). Weakened drive in n-channel pass transistors 5a, 5b due to PBTI can exacerbate this weakness in read current.
SRAM cells that exhibit PBTI and NBTI are vulnerable to a similar failure mechanism, referred to in the art as a retention stability failure. This failure is manifest by the cell being unable to retain its stored data state at a reduced power supply voltage level. As known in the art, many SRAM memories are expected to provide the user with a low power “retention mode” in which the power supply voltage applied to the memory array is reduced (during which time the memory is not available for immediate access). The reduced power supply voltage of course reduces the standby power consumed by the memory. As such, the ability of the cells in the memory array to retain their stored data states in retention mode is of importance. Indeed, the retention performance of the weakest cell in the array effectively determines the lowest power supply voltage available in retention mode, and thus the extent to which power consumption can be reduced in this mode. Weakened drive capability due to PBTI in one of the driver transistors, or weakened drive capability due to NBTI on one of the load transistors, contributes to poorer retention capability of an SRAM cell because of the resulting weakness with which the levels at the corresponding storage nodes are held by those devices.
Another failure mechanism that can result from PBTI and NBTI degradation is a write failure, which occurs when an addressed SRAM cell does not change its stored state in response to a write of the opposite data state from that stored. Write failures are the converse of read stability failures—while a read stability failure occurs if a cell changes its state too easily, a write failure occurs if a cell is too stubborn in changing its state, specifically by the write circuitry being unable to pull down the storage node that is currently latched to a high voltage.
For example, if cell 2 of FIG. 1 is storing a “0” data state, a high logic level will be present at storage node SNB. If pass transistor 5b has degraded due to PBTI, its drive current will have weakened and thus will reduce the ability of the low-side bit line BLBk to overcome the drive of load transistor 3b to write the opposite “1” data state. In addition, if driver transistor 4b has weakened due to PBTI, the effect of feedback from storage node SNT being pulled high by load transistor 3a during this write cycle will be reduced, further reducing the writeability of cell 2. NBTI degradation at load transistor 3a will also be reflected in a potential write failure (i.e., a write from “0” to “1”) by reducing its ability to pull storage node SNT high in response to storage node SNB being pulled low by bit line BLBk.
In each case, it is contemplated that the memory cells most vulnerable to the effects of PBTI or NBTI degradation are those cells that already have a device mismatch or other asymmetry in their manufacture. As mentioned above, such mismatches and asymmetries are more pronounced given the increased variability in the electrical characteristics observed for transistors having extremely small feature sizes, particularly in memories that are designed at or near their circuit design limits.
The increased level of reliability required of modern integrated circuits has necessitated the use of time-zero screens to remove (or repair, by way of redundant memory cells and circuit functions) those devices that are vulnerable to failure over the expected operating life of the device. In the sub-micron CMOS SRAM context, manufacturing test flows now commonly include screens to identify or replace those memory cells that are close to a pass/fail threshold at manufacture, within a margin corresponding to the expected PBTI or NBTI drift over the desired operating life. A conventional approach in such screening is to apply “guardbands” on certain applied voltages during functional or parametric tests of circuit functions. In many cases, guardbanded voltages are implemented to account for the temperature dependence of circuit behavior, to enable the manufacturer to perform functional testing at one temperature (preferably room temperature) with confidence that the circuit will perform according to specification over the full specified temperature range, over the expected operating life. As known in the art, it is becoming increasingly difficult to design the appropriate test “vectors” (i.e., combinations of bias and internal circuit voltages, and other test conditions) that identify devices that are vulnerable to failure over time and temperature, without significant yield loss of devices that would not fail over operating life yet fail the screen at the applied guardbanded test vectors.
Copending U.S. application Ser. No. 13/189,675, filed Jul. 25, 2011, commonly assigned herewith and incorporated herein by reference, describes a screening method for testing solid-state memories for the effects of long-term shift due to NBTI in combination with random telegraph noise (RTN), in the context of SRAM cells As described in that application, each memory cell in the array is functionally tested with a bias voltage (e.g., the cell power supply voltage) at a first guardband that is sufficient to account for worst case long-term shift and RTN effects. Cells failing the first guardband test are then repeatedly tested with the bias voltage at a second guardband that is less severe than the first; those previously failed cells that pass this second guardband are considered to not be vulnerable to RTN effects. This approach avoids the over-screening of conventional test methods that apply an unduly severe guardband, while still identifying vulnerable memory cells in the population for repair or as failed devices.
By way of further background, it is known in the art to apply a voltage higher than the power supply voltage to the body nodes of the p-channel load transistors during the test of SRAM arrays. This condition is referred to in the art as a “reverse back-bias” condition, and is typically applied to the n-well regions in which the load transistors are formed. As fundamental in the art, this reverse back-bias voltage has the effect of increasing the threshold voltage of the load transistors, and thus reducing their source-drain drive at a given source-drain voltage and gate-source voltage. Such a test is performed with the intent of screening out cells that are vulnerable to increased threshold voltage over operating time caused by NBTI.
It has been discovered, in connection with this invention, that it is difficult to derive an accurate time-zero screen to identify those memory cells for which NBTI and PBTI degradation will cause read or write failures or read stability failures. To the extent that potential proxies for this effect are available, those proxies necessitate an excessively harsh screen margin (i.e., guardband) to meet modern reliability goals. The undue yield loss of devices that fail such a screen but would, in fact, not have degraded to failure, can be substantial.